@Article{ c_2,
	author = "P.G. Paulin and C. Pilkington and M. Langevin and E. Bensoudane and D. Lyonnard and O. Benny and B. Lavigueur and D. Lo and G. Beltrame and V. Gagne and G. Nicolescu",
	journal = "Very Large Scale Integration (VLSI) Systems, IEEE Transactions on",
	title = "Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia",
	year = "2006",
	month = "july ",
	volume = "14",
	number = "7",
	pages = "667--680",
	keywords = "2.5 Gbit/s, MPEG4 decoder, MultiFlex system, distributed system object component, homogeneous platform programming environment, multimedia computing, multiprocessor SoC platform, multiprocessor interconnection, networking, parallel programming models, shared memory, symmetrical multiprocessing, system-on-chip, hardware-software codesign, multiprocessing systems, parallel programming, system-on-chip",
	doi = "10.1109/TVLSI.2006.878259",
	ISSN = "1063-8210"
}

@InProceedings{ c_3,
	author = "G. Beltrame and D. Sciuto and C. Silvano and D. Lyonnard and C. Pilkington",
	title = "Exploiting TLM and object introspection for system-level simulation",
	booktitle = "DATE '06: Proceedings of the conference on Design, automation and test in Europe",
	year = "2006",
	isbn = "3-9810801-0-6",
	pages = "100--105",
	location = "Munich, Germany",
	publisher = "European Design and Automation Association",
	address = "3001 Leuven, Belgium, Belgium"
}

@InProceedings{ c_4,
	author = "R. {Le Moigne} and O. Pasquier and J-P. Calvez",
	title = "A Generic RTOS Model for Real-time Systems Simulation with SystemC",
	booktitle = "DATE '04: Proceedings of the conference on Design, automation and test in Europe",
	year = "2004",
	isbn = "0-7695-2085-5-3",
	pages = "30082",
	publisher = "IEEE Computer Society",
	address = "Washington, DC, USA"
}

@InProceedings{ c_5,
	author = "E. Huck and B. Miramond and F. Verdier",
	title = "A Modular SystemC RTOS Model for Embedded Services Exploration ",
	booktitle = "First European Workshop on Design and Architectures for Signal and Image Processing (DASIP)",
	month = "nov.",
	year = "2007",
	publisher = "ECSI",
	address = "Grenoble, France",
	keywords = "RTOS Model, SystemC, MP-R-SoC",
	url = "http://publi-etis.ensea.fr/2007/HMV07"
}

@InProceedings{ c_6,
	author = "Andreas Gerstlauer and Haobo Yu and Daniel D. Gajski",
	title = "RTOS Modeling for System Level Design",
	booktitle = "DATE '03: Proceedings of the conference on Design, Automation and Test in Europe",
	year = "2003",
	isbn = "0-7695-1870-2",
	pages = "10130",
	publisher = "IEEE Computer Society",
	address = "Washington, DC, USA"
}

@InProceedings{ c_7,
	author = "Hector Posadas and Jes{\'u}s {\'A}damez and Pablo S{\'a}nchez and Eugenio Villar and Francisco Blasco",
	title = "POSIX modeling in SystemC",
	booktitle = "ASP-DAC '06: Proceedings of the 2006 Asia and South Pacific Design Automation Conference",
	year = "2006",
	isbn = "0-7803-9451-8",
	pages = "485--490",
	location = "Yokohama, Japan",
	doi = "http://doi.acm.org/10.1145/1118299.1118418",
	publisher = "IEEE Press",
	address = "Piscataway, NJ, USA"
}

@InProceedings{ c_8,
	author = "Bruno Albertini and Sandro Rigo and Guido Araujo and Cristiano Araujo and Edna Barros and Willians Azevedo",
	title = "A computational reflection mechanism to support platform debugging in SystemC",
	booktitle = "CODES+ISSS '07: Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis",
	year = "2007",
	isbn = "978-1-59593-824-4",
	pages = "81--86",
	location = "Salzburg, Austria",
	doi = "http://doi.acm.org/10.1145/1289816.1289838",
	publisher = "ACM",
	address = "New York, NY, USA"
}

@Article{ c_9,
	author = "Hiren D. Patel and Deepak Mathaikutty and David Berner and Sandeep K. Shukla",
	title = "CARH: service-oriented architecture for validating system-level designs",
	journal = "IEEE Trans. on CAD of Integrated Circuits and Systems",
	volume = "25",
	number = "8",
	year = "2006",
	pages = "1458--1474",
	ee = "http://doi.ieeecomputersociety.org/10.1109/TCAD.2005.857315",
	bibsource = "DBLP, http://dblp.uni-trier.de"
}

@Article{ p_60,
	author = "S. Mohanty and V. K. Prasanna and S. Neema and J. Davis",
	title = "Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation",
	journal = "SIGPLAN Not.",
	volume = "37",
	number = "7",
	year = "2002",
	issn = "0362-1340",
	pages = "18--27",
	doi = "http://doi.acm.org/10.1145/566225.513835",
	publisher = "ACM",
	address = "New York, NY, USA"
}

@Article{ p_40,
	author = "Cagkan Erbas and Andy D. Pimentel and Mark Thompson and Simon Polstra",
	title = "A framework for system-level modeling and simulation of embedded systems architectures",
	journal = "EURASIP J. Embedded Syst.",
	volume = "2007",
	number = "1",
	year = "2007",
	issn = "1687-3955",
	pages = "2--2",
	doi = "http://dx.doi.org/10.1155/2007/82123",
	publisher = "Hindawi Publishing Corp.",
	address = "New York, NY, United States"
}

@Article{ p_77,
	author = "Andy D. Pimentel and Cagkan Erbas and Simon Polstra",
	title = "A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels",
	journal = "IEEE Trans. Comput.",
	volume = "55",
	number = "2",
	year = "2006",
	issn = "0018-9340",
	pages = "99--112",
	doi = "http://dx.doi.org/10.1109/TC.2006.16",
	publisher = "IEEE Computer Society",
	address = "Washington, DC, USA"
}

@InProceedings{ p_83,
	author = "Kamana Sigdel and Mark Thompson and Andy D. Pimentel and Todor Stefanov and Koen Bertels",
	title = "System-Level Design Space Exploration of Dynamic Reconfigurable Architectures",
	booktitle = "SAMOS '08: Proceedings of the 8th international workshop on Embedded Computer Systems",
	year = "2008",
	isbn = "978-3-540-70549-9",
	pages = "279--288",
	location = "Samos, Greece",
	doi = "http://dx.doi.org/10.1007/978-3-540-70550-5\_31",
	publisher = "Springer-Verlag",
	address = "Berlin, Heidelberg"
}

@Misc{ sematech_international_2004,
	title = "International technology roadmap for semiconductors {(ITRS),} 2004 update, design.",
	url = "http://www.itrs.net/",
	author = "{SEMATECH}",
	year = "2004",
	howpublished = "http://www.itrs.net/"
}

@Book{ martin_esl_2007,
	title = "{ESL} Design and Verification: A Prescription for Electronic System Level Methodology",
	isbn = "0123735513",
	shorttitle = "{ESL} Design and Verification",
	publisher = "Morgan Kaufmann",
	author = "Grant Martin and Brian Bailey and Andrew Piziali",
	month = mar,
	year = "2007"
}

@InProceedings{ cai_transaction_2003,
	title = "Transaction Level Modeling: an Overview",
	isbn = "1-58113-742-7",
	location = "Newport Beach, {CA,} {USA}",
	booktitle = "{CODES+ISSS} '03: Proceedings of the 1st {IEEE/ACM/IFIP} international conference on Hardware/software codesign and system synthesis",
	author = "L. Cai and D. Gajski",
	year = "2003",
	keywords = "Transaction Level Modeling",
	pages = "19--24"
}

@Article{ domer_system-chip_2008,
	title = "System-on-chip environment: a {SpecC-based} framework for heterogeneous {MPSoC} design",
	volume = "2008",
	shorttitle = "System-on-chip environment",
	url = "http://portal.acm.org/citation.cfm?id=1463089",
	abstract = "The constantly growing complexity of embedded systems is a challenge that drives the development of novel design automation techniques. C-based system-level design addresses the complexity challenge by raising the level of abstraction and integrating the design processes for the heterogeneous system components. In this article, we present a comprehensive design framework, the system-on-chip environment {(SCE)} which is based on the influential {SpecC} language and methodology. {SCE} implements a top-down system design flow based on a specify-explore-refine paradigm with support for heterogeneous target platforms consisting of custom hardware components, embedded software processors, dedicated {IP} blocks, and complex communication bus architectures. Starting from an abstract specification of the desired system, models at various levels of abstraction are automatically generated through successive step-wise refinement, resulting in a pin-and cycle-accurate system implementation. The seamless integration of automatic model generation, estimation, and verification tools enables rapid design space exploration and efficient {MPSoC} implementation. Using a large set of industrial-strength examples with a wide range of target architectures, our experimental results demonstrate the effectiveness of our framework and show significant productivity gains in design time.",
	journal = "{EURASIP} J. Embedded Syst.",
	author = "Rainer Domer and Andreas Gerstlauer and Junyu Peng and Dongwan Shin and Lukai Cai and Haobo Yu and Samar Abdi and Daniel D. Gajski",
	year = "2008",
	pages = "1--13"
}

@Article{ keutzer_system-level_2000,
	title = "System-level design: orthogonalization of concerns and platform-based design",
	volume = "19",
	issn = "0278-0070",
	shorttitle = "System-level design",
	doi = "10.1109/43.898830",
	abstract = "System-level design issues become critical as implementation technology evolves toward increasingly complex integrated circuits and the time-to-market pressure continues relentlessly. To cope with these issues, new methodologies that emphasize re-use at all levels of abstraction are a ?must?, and this is a major focus of our work in the Gigascale Silicon Research Center. We present some important concepts for system design that are likely to provide at least some of the gains in productivity postulated above. In particular, we focus on a method that separates parts of the design process and makes them nearly independent so that complexity could be mastered. In this domain, architecture-function co-design and communication-based design are introduced and motivated. Platforms are essential elements of this design paradigm. We define system platforms and we argue about their use and relevance. Then we present an application of the design methodology to the design of wireless systems. Finally, we present a new approach to platform-based design called modern embedded systems, compilers, architectures and languages, based on highly concurrent and software programmable architectures and associated design tools",
	number = "12",
	journal = "{Computer-Aided} Design of Integrated Circuits and Systems, {IEEE} Transactions on",
	author = "K. Keutzer and {A.R.} Newton and {J.M.} Rabaey and A. {Sangiovanni-Vincentelli}",
	year = "2000",
	keywords = "architecture-function co-design, circuit {CAD, } communication-based design, compilers, complex integrated circuits, concurrent architectures, design methodology, design tools, integrated circuit design, platform-based design, program compilers, software programmable architecture, system-level design, wireless system design",
	pages = "1523--1543"
}

@InProceedings{ cescirio_component-based_2002,
	title = "Component-based design approach for multicore {SoCs}",
	isbn = "{0738-100X}",
	doi = "{10.1109/DAC.2002.1012730}",
	abstract = "This paper presents a high-level component-based methodology and design environment for application-specific multicore {SoC} architectures. Component-based design provides primitives to build complex architectures from basic components. This bottom up approach allows design-architects to explore efficient custom solutions with best performances. This paper presents a high-level component-based methodology and design environment for application-specific multicore {SoC} architectures. The system specifications are represented as a virtual architecture described in a {SystemC-like} model and annotated with a set of configuration parameters. Our component-based design environment provides automatic wrapper-generation tools able to synthesize hardware interfaces, device drivers, and operating systems that implement a high-level interconnect {API.} This approach, experimented over a {VDSL} system, shows a drastic design time reduction without any significant efficiency loss in the final circuit.",
	booktitle = "Design Automation Conference, 2002. Proceedings. 39th",
	author = "W. Cescirio and A. Baghdadi and L. Gauthier and D. Lyonnard and G. Nicolescu and Y. Paviot and S. Yoo and {A.A.} Jerraya and M. {Diaz-Nava}",
	year = "2002",
	keywords = "application program interfaces, application-specific multicore {SoC} architectures, {ASICs, } automatic wrapper-generation tools, bottom-up approach, circuit {CAD, } component-based design approach, configuration parameters, design time reduction, device drivers, hardware interfaces, high-level component-based methodology, high-level design environment, high-level interconnect {API, } integrated circuit design, system-on-chip, {SystemC-like} model, {VDSL} system, virtual architecture",
	pages = "789--794"
}

@Article{ chevalier_systemc_2006,
	title = "A {SystemC} Refinement Methodology for Embedded Software",
	volume = "23",
	url = "http://portal.acm.org/citation.cfm?id=1130718.1130790",
	abstract = "Editor's note: This article presents a design environment that provides an interface for user-written {SystemC} modules that model application software to make calls to a real-time operating system {(RTOS)} kernel and cosimulate with user-written {SystemC} hardware modules. The environment also facilitates successive refinement through three abstraction layers for hardware-software codesign suitable for embedded-system design. {--Sandeep} Shukla, Virginia Tech",
	number = "2",
	journal = "{IEEE} Des. Test",
	author = "Jerome Chevalier and Maxime {de Nanclas} and Luc Filion and Olivier Benny and Mathieu Rondonneau and Guy Bois and El Mostapha Aboulhamid",
	year = "2006",
	keywords = "integration, modeling hardware/software interfaces, real-time and embedded systems, system architectures",
	pages = "148--158"
}

@Article{ magnusson_simics-full_2002,
	title = "Simics: A full system simulation platform",
	volume = "35",
	issn = "0018-9162",
	shorttitle = "Simics",
	doi = "10.1109/2.982916",
	abstract = "Full system simulation seeks to strike a balance between accuracy and performance. Many of its possibilities have been obvious to practitioners in both academia and industry for quite some time, perhaps decades, but Simics supports more of these possibilities within a single framework than other tools do. Simics is a platform for full system simulation that can run actual firmware and completely unmodified kernel and driver code. It is sufficiently abstract to achieve tolerable performance levels, and it provides both functional accuracy for running commercial workloads and sufficient timing accuracy to interface to detailed hardware models. Simics can also run a heterogeneous network of systems from different vendors within the same framework. Exceptionally fast, Simics can easily add new components and leverage older ones within a practical abstraction level. It offers a platform with a rich {API} and a powerful scripting environment for use in a broad range of applications",
	number = "2",
	journal = "Computer",
	author = "{P.S.} Magnusson and M. Christensson and J. Eskilson and D. Forsgren and G. Hallberg and J. Hogberg and F. Larsson and A. Moestedt and B. Werner",
	year = "2002",
	keywords = "digital simulation, full system simulator, heterogeneous net-work of systems, performance, Simics, virtual machines",
	pages = "50--58"
}

@Article{ thoen_enabling_2001,
	title = "Enabling Early Software Development through Virtual System Prototyping",
	journal = "The {EDN} System Design Series",
	author = "Filip Thoen",
	year = "2001",
	pages = "pp. 32--36"
}

@InProceedings{ dehon_reconfigurable_1999,
	address = "New Orleans, Louisiana, United States",
	title = "Reconfigurable computing: what, why, and implications for design automation",
	isbn = "1-58133-109-7",
	shorttitle = "Reconfigurable computing",
	url = "http://portal.acm.org/citation.cfm?id=310009",
	doi = "10.1145/309847.310009",
	abstract = "Note: {OCR} errors may be found in this Reference List extracted from the full text article. {ACM} has opted to expose the complete List rather than only correct and linked references.",
	booktitle = "{DAC} '99: Proceedings of the 36th annual {ACM/IEEE} Design Automation Conference",
	publisher = "{ACM}",
	author = "Andr{\`e} {DeHon} and John Wawrzynek",
	year = "1999",
	pages = "610--615"
}

@Article{ todman_reconfigurable_2005,
	title = "{Reconfigurable Computing: Architectures and Design Methods}",
	journal = "Computers and Digital Techniques, {IEEE} Proceedings",
	volume = "152",
	number = "2",
	author = "Timothy Todman and George Constantinides and Steve Wilton and Peter Cheung and Wayne Luk and Oskar Mencer",
	pages = "193--205",
	month = "March",
	year = "2005",
	url = "http://pubs.doc.ic.ac.uk/reconfigurable-computing/",
	abstract = "Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix {II} and Xilinx Virtex 4 {FPGA} devices. The authors identify major trends in general-purpose and special-purpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70\% energy savings over microprocessor implementations for specific applications."
}

@Article{ compton_reconfigurable_2002,
	title = "Reconfigurable computing: a survey of systems and software",
	volume = "34",
	shorttitle = "Reconfigurable computing",
	url = "http://portal.acm.org/citation.cfm?id=508353",
	doi = "10.1145/508352.508353",
	abstract = "Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.",
	number = "2",
	journal = "{ACM} Comput. Surv.",
	author = "Katherine Compton and Scott Hauck",
	year = "2002",
	keywords = "automatic design, field-programmable, fpga, manual design, reconfigurable computing, reconfigurable systems",
	pages = "171--210"
}

@InProceedings{ givargis_system-level_2001,
	title = "System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip",
	doi = "{10.1109/ICCAD.2001.968593}",
	abstract = "Provides a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip {(SOC)} architecture to find all Pareto-optimal configurations. These configurations represent the range of meaningful power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application mapped onto the {SOC} architecture. The approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. The authors have successfully incorporated the technique into the parameterized {SOC} tuning environment {(Platune)} and applied it to a number of applications",
	booktitle = "Computer Aided Design, 2001. {ICCAD} 2001. {IEEE/ACM} International Conference on",
	author = "T. Givargis and F. Vahid and J. Henkel",
	year = "2001",
	keywords = "application specific integrated circuits, circuit {CAD, } circuit optimisation, circuit tuning, configuration space, fixed application, integrated circuit design, low-power system design, network parameters, parameter dependencies, parameter values, parameterized system-on-a-chip architecture, Pareto distribution, Pareto-optimal configurations, Platune, power-performance tradeoffs, {SOC} architecture, system-level exploration, tuning environment",
	pages = "25--30"
}

@Article{ mohanty_rapid_2002,
	title = "Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation",
	volume = "37",
	url = "http://portal.acm.org/citation.cfm?id=566225.513835&coll=&dl=",
	doi = "10.1145/566225.513835",
	abstract = "In addition to integrating different Intellectual Property cores, heterogeneous embedded systems provide several architecture knobs such as voltage, operating frequency, configuration, etc. that can be varied to optimize performance. Such flexibilities results in a large design space making system optimization a very challenging task. Moreover, such systems operate in mobile and other power constrained environments. Therefore, in addition to rapid exploration of a large design space a designer has to optimize both time and energy performance. To address these issues, we propose a hierarchical design space exploration methodology. Our methodology initially uses symbolic constraint satisfaction to rapidly prune the design space. This pruning process is followed by a system wide performance estimation to further reduce the number of candidate designs. Finally, detailed simulation using low-level simulators are performed to select an appropriate design. Our methodology is implemented by integrating two tools, {DESERT} and {HiPerE,} into the M model based Integrated {simuLAtioN} {(MILAN)} framework. {DESERT} uses Ordered Binary Decision Diagrams based symbolic search to rapidly explore a large design space and identifies candidate designs that meet the user specified performance constraints. {HiPerE} provides rapid estimation of system wide energy and latency based on component level simulations and also facilitates energy optimization. {MILAN} provides the required modeling support for these tools and also facilitates component specific multi-granular simulations through seamless integration of various simulators.",
	number = "7",
	journal = "{SIGPLAN} Not.",
	author = "S. Mohanty and V. K. Prasanna and S. Neema and J. Davis",
	year = "2002",
	keywords = "binary decision diagram, design space, model integrated computing, modeling, multi-granular simulation, symbolic search",
	pages = "18--27"
}

@InProceedings{ palesi_multi-objective_2002,
	address = "Estes Park, Colorado",
	title = "Multi-objective design space exploration using genetic algorithms",
	isbn = "1-58113-542-4",
	url = "http://portal.acm.org/citation.cfm?id=774804",
	doi = "10.1145/774789.774804",
	abstract = "In this work, we provide a technique for efficiently exploring a parameterized system-on-a-chip {(SoC)} architecture to find all Pareto-optimal configurations in a multi-objective design space. Globally, our approach uses a parameter dependency model of our target parameterized {SoC} architecture to extensively prune non-optimal sub-spaces. Locally, our approach applies Genetic Algorithms {(GAs)} to discover Pareto-optimal configurations within the remaining design points. The computed Pareto-optimal configurations will represent the range of performance (e.g., timing and power) tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the parameterized {SoC} architecture. We have successfully applied our technique to explore Pareto-optimal configurations for a number of applications mapped on a parameterized {SoC} architecture.",
	booktitle = "{CODES} '02: Proceedings of the tenth international symposium on Hardware/software codesign",
	publisher = "{ACM}",
	author = "Maurizio Palesi and Tony Givargis",
	year = "2002",
	keywords = "design space exploration, low power design, pareto-optimal configurations, system-on-a-chip architectures",
	pages = "67--72"
}

@Article{ jaszkiewicz_multiple_2001,
	title = "Multiple Objective Metaheuristic Algorithms For Combinatorial Optimization",
	url = "http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.17.6307",
	author = "Andrzej Jaszkiewicz and Przewodniczacy Komitetu Redakcyjnego",
	year = "2001"
}

@Article{ yi_simulation_2006,
	title = "Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations",
	volume = "55",
	issn = "0018-9340",
	shorttitle = "Simulation of computer architectures",
	doi = "{10.1109/TC.2006.44}",
	abstract = "Simulators have become an integral part of the computer architecture research and design process. Since they have the advantages of cost, time, and flexibility, architects use them to guide design space exploration and to quantify the efficacy of an enhancement. However, long simulation times and poor accuracy limit their effectiveness. To reduce the simulation time, architects have proposed several techniques that increase the simulation speed or throughput. To increase the accuracy, architects try to minimize the amount of error in their simulators and have proposed adding statistical rigor to their simulation methodology. Since a wide range of approaches exist and since many of them overlap, this paper describes, classifies, and compares them to aid the computer architect in selecting the most appropriate one.",
	number = "3",
	journal = "Computers, {IEEE} Transactions on",
	author = "{J.J.} Yi and {D.J.} Lilja",
	year = "2006",
	keywords = "benchmark testing, computer architecture, computer architecture simulation, digital simulation, evaluation, measurement, measurement techniques, modeling, modeling of computer architecture, modeling techniques, multiple-processor systems, Simulation, simulation of multiple-processor systems.",
	pages = "268--280"
}

@Book{ weise_global_2007,
	edition = "July 16, 2007",
	title = "{Global Optimization Algorithms - Theory and Application}",
	url = "http://www.it-weise.de/projects/book.pdf",
	publisher = "Thomas Weise",
	author = "Thomas Weise",
	month = jul,
	year = "2007",
	note = "Published: Online as e-book available at http://www.it-weise.de/projects/book.pdf."
}

@InProceedings{ dick_mogac_multi-objective_1997,
	address = "San Jose, California, United States",
	title = "{MOGAC:} a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems",
	isbn = "0-8186-8200-0",
	shorttitle = "{MOGAC}",
	url = "http://portal.acm.org/citation.cfm?id=266388.266544&coll=&dl=&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD",
	abstract = "In this paper, we present a hardware-software co-synthesis system, called {MOGAC,} that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. {MOGAC} synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. {MOGAC} places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multi-rate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single co-synthesis run to produce multiple designs which trade off different architectural features. Experimental results indicate that {MOGAC} has advantages over previous work in terms of solution quality and running time.",
	booktitle = "{ICCAD} '97: Proceedings of the 1997 {IEEE/ACM} international conference on Computer-aided design",
	publisher = "{IEEE} Computer Society",
	author = "Robert P. Dick and Niraj K. Jha",
	year = "1997",
	keywords = "co-design, co-synthesis, embedded system, genetic algorithm, hardware-software, low power, multiobjective",
	pages = "522--529"
}

@Article{ mouhoub_mocdex_2006,
	title = "{MOCDEX:} multiprocessor on chip multiobjective design space exploration with direct execution",
	volume = "2006",
	shorttitle = "{MOCDEX}",
	url = "http://portal.acm.org/citation.cfm?id=1288235",
	abstract = "Fully integrated system level design space exploration methodologies are essential to guarantee efficiency of future large scale system on programmable chip. Each design step in the design flow from system architecture to place and route represents an optimization problem. So far, different tools (computer architecture, design automation) are used to address each problem separately with at best estimation techniques from one level to another. This approach ignores the various and very diverse vertical relations between distinct levels parameters and provides at best local optimization solutions at each step. Due to the large scale of {SoC,} system level design methodologies need to tackle the system design process as a global optimization problem by fully integrating physical design in the design space exploration. We propose {MOCDEX,} a multiobjective design space exploration methodology, for multiprocessor on chip which closes the gap between these associated tools in a fully integrated approach and with hardware in the loop. A case study of a 4-way multiprocessor demonstrates the validity of our approach.",
	number = "1",
	journal = "{EURASIP} J. Embedded Syst.",
	author = "Riad Ben Mouhoub and Omar Hammami",
	year = "2006",
	pages = "12--12"
}

@Article{ palermo_multi-objective_2005,
	title = "Multi-objective design space exploration of embedded systems",
	volume = "1",
	url = "http://portal.acm.org/citation.cfm?id=1233750",
	abstract = "In this paper, we address the problem of the efficient exploration of the architectural design space for parameterized embedded systems. The exploration problem is multi-objective (e.g., energy and delay), so the main goal of this work is to find a good approximation of the Pareto-optimal configurations representing the best energy/delay trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration {(DSE)} framework to simulate the target system and to dynamically profile the target applications. In the proposed {DSE} framework, a set of heuristic algorithms have been analyzed to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit. Once the approximated Pareto set has been built, the designer can quickly select the best system configuration satisfying the constraints. Experimental results, derived from the application of the proposed {DSE} framework to a superscalar architecture, show that the exploration time can be reduced by three orders of magnitude with respect to the full search approach, while maintaining a good level of accuracy.",
	number = "3",
	journal = "J. Embedded Comput.",
	author = "Gianluca Palermo and Cristina Silvano and Vittorio Zaccaria",
	year = "2005",
	keywords = "design space exploration, low-power design, platform-based design",
	pages = "305--316"
}

@InProceedings{ mostaghim_covering_2004,
	title = "Covering Pareto-optimal fronts by subswarms in multi-objective particle swarm optimization",
	volume = "2",
	abstract = "Covering the whole set of Pareto-optimal solutions is a desired task of multiobjective optimization methods. Because in general it is not possible to determine this set, a restricted amount of solutions are typically delivered in the output to decision makers. We propose a method using multiobjective particle swarm optimization to cover the Pareto-optimal front. The method works in two phases. In phase 1 the goal is to obtain a good approximation of the Pareto-front. In a second run subswarms are generated to cover the Pareto-front. The method is evaluated using different test functions and compared with an existing covering method using a real world example in antenna design.",
	booktitle = "Evolutionary Computation, 2004. {CEC2004.} Congress on",
	author = "S. Mostaghim and J. Teich",
	year = "2004",
	keywords = "antenna design, antennas, multiobjective optimization method, multiobjective particle swarm optimization, Pareto optimisation, Pareto-optimal fronts, Pareto-optimal solutions",
	pages = "1404--1411 Vol.2"
}

@Article{ zitzler_performance_2003,
	title = "Performance assessment of multiobjective optimizers: an analysis and review",
	volume = "7",
	issn = "{1089-778X}",
	shorttitle = "Performance assessment of multiobjective optimizers",
	doi = "{10.1109/TEVC.2003.810758}",
	abstract = "An important issue in multiobjective optimization is the quantitative comparison of the performance of different algorithms. In the case of multiobjective evolutionary algorithms, the outcome is usually an approximation of the Pareto-optimal set, which is denoted as an approximation set, and therefore the question arises of how to evaluate the quality of approximation sets. Most popular are methods that assign each approximation set a vector of real numbers that reflect different aspects of the quality. Sometimes, pairs of approximation sets are also considered. In this study, we provide a rigorous analysis of the limitations underlying this type of quality assessment. To this end, a mathematical framework is developed which allows one to classify and discuss existing techniques.",
	number = "2",
	journal = "Evolutionary Computation, {IEEE} Transactions on",
	author = "E. Zitzler and L. Thiele and M. Laumanns and {C.M.} Fonseca and {V.G.} {da Fonseca}",
	year = "2003",
	keywords = "approximation set, approximation theory, evolutionary algorithms, multiobjective optimization, Pareto-optimal set, performance assessment, quality indicator",
	pages = "117--132"
}

@Article{ givargis_platune-tuning_2002,
	title = "Platune: a tuning framework for system-on-a-chip platforms",
	volume = "21",
	issn = "0278-0070",
	shorttitle = "Platune",
	doi = "{10.1109/TCAD.2002.804107}",
	abstract = "System-on-a-chip {(SOC)} platform manufacturers are increasingly adding configurable features that provide power and performance flexibility in order to increase a platform's applicability. This paper presents a framework, called Platune, for performance and power tuning of one such {SOC} platform. Platune is used to simulate an embedded application that is mapped onto the {SOC} platform and output performance and power metrics for any configuration of the {SOC} platform. Furthermore, Platune is used to automatically explore the large configuration space of such an {SOC} platform. The versatility, in terms of accuracy and speed of exploration, of Platune is demonstrated experimentally using three large benchmark examples. The power estimation techniques for processors, caches, memories, buses, and peripherals combined with the design space exploration algorithm deployed by Platune form a methodology for design-of tuning frameworks for parameterized {SOC} platforms in general.",
	number = "11",
	journal = "{Computer-Aided} Design of Integrated Circuits and Systems, {IEEE} Transactions on",
	author = "T. Givargis and F. Vahid",
	year = "2002",
	keywords = "circuit {CAD, } circuit simulation, design space exploration algorithm, embedded application simulation, exploration speed, integrated circuit design, low-power design, low-power electronics, output performance, parameter tuning, platform-based design, Platune, power estimation techniques, power metrics, {SOC} platform, system-on-a-chip platforms, system-on-chip, tuning framework",
	pages = "1317--1327"
}

@Article{ fornaciari_sensitivity-based_2002,
	title = "A {Sensitivity-Based} Design Space Exploration Methodology for Embedded Systems",
	volume = "7",
	url = "http://dx.doi.org/10.1023/A:1019791213967",
	doi = "{10.1023/A:1019791213967}",
	abstract = "In this paper, we propose a system-level design methodology for the efficient exploration of the architectural parameters of the memory sub-systems, from the energy-delay joint perspective. The aim is to find the best configuration of the memory hierarchy without performing the exhaustive analysis of the parameters space. The target system architecture includes the processor, separated instruction and data caches, the main memory, and the system buses. To achieve a fast convergence toward the near-optimal configuration, the proposed methodology adopts an iterative local-search algorithm based on the sensitivity analysis of the cost function with respect to the tuning parameters of the memory sub-system architecture. The exploration strategy is based on the {Energy-Delay} Product {(EDP)} metric taking into consideration both performance and energy constraints. The effectiveness of the proposed methodology has been demonstrated through the design space exploration of a real-world case study: the optimization of the memory hierarchy of a {MicroSPARC2-based} system executing the set of Mediabench benchmarks for multimedia applications. Experimental results have shown an optimization speedup of 2 orders of magnitude with respect to the full search approach, while the near-optimal system-level configuration is characterized by a distance from the optimal full search configuration in the range of 2\%.",
	number = "1",
	journal = "Design Automation for Embedded Systems",
	author = "William Fornaciari and Donatella Sciuto and Cristina Silvano and Vittorio Zaccaria",
	year = "2002",
	pages = "7--33"
}

@InProceedings{ sheldon_soft-core_2007,
	title = "Soft-core Processor Customization using the Design of Experiments Paradigm",
	abstract = "Parameterized components are becoming more commonplace in system design. The process of customizing parameter values for a particular application, called tuning, can be a challenging task for a designer. Here we focus on the problem of tuning a parameterized soft-core microprocessor to achieve the best performance on a particular application, subject to size constraints. We map the tuning problem to a well-established statistical paradigm called design of experiments {(DoE),} which involves the design of a carefully selected set of experiments and a sophisticated analysis that has the objective to extract the maximum amount of information about the effects of the input parameters on the experiment. We apply the {DoE} method to analyze the relation between input parameters and the performance of a soft-core microprocessor for a particular application, using only a small number of synthesis/execution runs. The information gained by the analysis in turn drives a soft-core tuning heuristic. We show that using {DoE} to sort the parameters in order of impact results in application speedups of 6times-17times versus an un-tuned base soft-core. When compared to a previous single-factor tuning method, the {DoE-based} method achieves 3times-6times application speedups, while requiring about the same tuning runtime. We also show that tuning runtime can be reduced by 40-45\% by using predictive tuning methods already built into a {DoE} tool",
	booktitle = "Design, Automation \& Test in Europe Conference \& Exhibition, 2007. {DATE} '07",
	author = "D. Sheldon and F. Vahid and S. Lonardi",
	year = "2007",
	keywords = "design of experiments, microprocessor chips, soft core microprocessor, system design, tuning heuristic",
	pages = "1--6"
}

@Book{ montgomery_design_2000,
	edition = "5",
	title = "Design and Analysis of Experiments, 5th Edition",
	isbn = "0471316490",
	publisher = "Wiley",
	author = "Douglas C. Montgomery",
	month = jun,
	year = "2000"
}

@InProceedings{ palermo_efficient_2008,
	title = "An efficient design space exploration methodology for multiprocessor {SoC} architectures based on response surface methods",
	abstract = "Multi-processor system on-chip {(MPSoC)} architectures are currently designed by using a platform-based approach. In this approach, a wide range of platform parameters must be tuned to find the best trade-offs in terms of the selected figures of merit (such as energy, delay and area). This optimization phase is called design space exploration {(DSE)} and it generally consists of a multi-objective optimization {(MOO)} problem. The design space for an {MPSoC} architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the {MOO} problem for {MPSoC,} but they are characterized by low efficiency to identify the Pareto front. In this paper, an efficient {DSE} methodology is proposed leveraging traditional Design of Experiments {(DoE)} and response surface modeling {(RSM)} techniques. In particular, the {DoE} phase generates an initial plan of experiments used to create a coarse view of the target design space; a set of {RSM} techniques are then used to refine the exploration. This process is iteratively repeated until the target criterion (e.g. number of simulations) is satisfied. A set of experimental results are reported to trade-off accuracy and efficiency of the proposed techniques with actual workloads.",
	booktitle = "Embedded Computer Systems: Architectures, Modeling, and Simulation, 2008. {SAMOS} 2008. International Conference on",
	author = "G. Palermo and C. Silvano and V. Zaccaria",
	year = "2008",
	keywords = "design of experiments, design space exploration methodology, design-of-experiment, logic design, {MPSoC, } multiobjective optimization problem, multiprocessing systems, multiprocessor system on-chip architecture, Pareto optimisation, response surface method, system-on-chip",
	pages = "150--157"
}

@InProceedings{ lukasiewycz_efficient_2008,
	address = "Seoul, Korea",
	title = "Efficient symbolic multi-objective design space exploration",
	isbn = "978-1-4244-1922-7",
	url = "http://portal.acm.org/citation.cfm?id=1356969",
	abstract = "Nowadays many design space exploration tools are based on {Multi-Objective} Evolutionary Algorithms {(MOEAs).} Beside the advantages of {MOEAs,} there is one important drawback as {MOEAs} might fail in design spaces containing only a few feasible solutions or as they are often afflicted with premature convergence, i.e., the same design points are revisited again and again. Exact methods, especially Pseudo Boolean solvers {(PB} solvers) seem to be a solution. However, as typical design spaces are multi-objective, there is a need for multi-objective {PB} solvers. In this paper, we will formalize the problem of design space exploration as multi-objective 0--1 {ILP.} We will propose (1) a heuristic approach based on {PB} solvers and (2) a complete multi-objective {PB} solver based on a backtracking algorithm that incorporates the non-dominance relation from multi-objective optimization and is restricted to linear objective functions. First results from applying our novel multi-objective {PB} solver to synthetic problems will show its effectiveness in small sized design spaces as well as in large design spaces only containing a few feasible solutions. For non-linear and large problems, the proposed heuristic approach is outperforming common {MOEA} approaches. Finally, a real world example from the automotive area will emphasize the efficiency of the proposed algorithms.",
	booktitle = "{ASP-DAC} '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference",
	publisher = "{IEEE} Computer Society Press",
	author = "Martin Lukasiewycz and Michael Glau and Christian Haubelt and Jurgen Teich",
	year = "2008",
	pages = "691--696"
}

@Article{ ascia_efficient_2007,
	title = "Efficient design space exploration for application specific systems-on-a-chip",
	volume = "53",
	url = "http://portal.acm.org/citation.cfm?id=1244553",
	abstract = "A reduction in the time-to-market has led to widespread use of pre-designed parametric architectural solutions known as system-on-a-chip {(SoC)} platforms. A system designer has to configure the platform in such a way as to optimize it for the execution of a specific application. Very frequently, however, the space of possible configurations that can be mapped onto a {SoC} platform is huge and the computational effort needed to evaluate a single system configuration can be very costly. In this paper we propose an approach which tackles the problem of design space exploration {(DSE)} in both of the fronts of the reduction of the number of system configurations to be simulated and the reduction of the time required to evaluate (i.e., simulate) a system configuration. More precisely, we propose the use of Multi-objective Evolutionary Algorithms as optimization technique and Fuzzy Systems for the estimation of the performance indexes to be optimized. The proposed approach is applied on a highly parameterized {SoC} platform based on a parameterized {VLIW} processor and a parameterized memory hierarchy for the optimization of performance and power dissipation. The approach is evaluated in terms of both accuracy and efficiency and compared with several established {DSE} approaches. The results obtained for a set of multimedia applications show an improvement in both accuracy and exploration time.",
	number = "10",
	journal = "J. Syst. Archit.",
	author = "Giuseppe Ascia and Vincenzo Catania and Alessandro G. Di Nuovo and Maurizio Palesi and Davide Patti",
	year = "2007",
	keywords = "design space exploration, embedded system design, evolutionary computation, fuzzy estimation, multi-objective optimization, very long instruction word processor",
	pages = "733--750"
}

@Article{ ipek_efficient_2008,
	title = "Efficient architectural design space exploration via predictive modeling",
	volume = "4",
	url = "http://portal.acm.org/citation.cfm?id=1328195.1328196",
	doi = "10.1145/1328195.1328196",
	abstract = "Efficiently exploring exponential-size architectural design spaces with many interacting parameters remains an open problem: the sheer number of experiments required renders detailed simulation intractable. We attack this via an automated approach that builds accurate predictive models. We simulate sampled points, using results to teach our models the function describing relationships among design parameters. The models can be queried and are very fast, enabling efficient design tradeoff discovery. We validate our approach via two uniprocessor sensitivity studies, predicting {IPC} with only 1--2\&percnt; error. In an experimental study using the approach, training on 1\&percnt; of a {250-K-point} {CMP} design space allows our models to predict performance with only 4--5\&percnt; error. Our predictive modeling combines well with techniques that reduce the time taken by each simulation experiment, achieving net time savings of three-four orders of magnitude.",
	number = "4",
	journal = "{ACM} Trans. Archit. Code Optim.",
	author = "Engin Ipek and Sally A. {McKee} and Karan Singh and Rich Caruana and Bronis R. {de Supinski} and Martin Schulz",
	year = "2008",
	keywords = "artificial neural networks, design space exploration, performance prediction, sensitivity studies",
	pages = "1--34"
}

@Article{ neumann_efpga-asip_2008,
	author = "B. Neumann and T. Sydow and H. Blume and T. G. Noll",
	title = "Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs",
	journal = "J. Signal Process. Syst.",
	volume = "53",
	number = "1-2",
	year = "2008",
	issn = "1939-8018",
	pages = "129--143",
	doi = "http://dx.doi.org/10.1007/s11265-008-0211-9",
	publisher = "Kluwer Academic Publishers",
	address = "Hingham, MA, USA"
}

@InProceedings{ neumann_efpga-templ_2008,
	author = "B. Neumann and T. {von Sydow} and H. Blume and T. G. Noll",
	title = "Design flow for embedded FPGAs based on a flexible architecture template",
	booktitle = "DATE '08: Proceedings of the conference on Design, automation and test in Europe",
	year = "2008",
	isbn = "978-3-9810801-3-1",
	pages = "56--61",
	location = "Munich, Germany",
	doi = "http://doi.acm.org/10.1145/1403375.1403391",
	publisher = "ACM",
	address = "New York, NY, USA"
}

@Article{ balarin_metropolis-integrated_2003,
	title = "Metropolis: An Integrated Electronic System Design Environment",
	volume = "vol. 36",
	shorttitle = "Metropolis",
	abstract = "Today, the design chain lacks adequate support, with most system-level designers using a collection of unlinked tools. The implementation then proceeds with informal techniques involving numerous human-language interactions that create unnecessary and unwanted iterations among groups of designers in different companies or different {divisions.The} move toward programmable platforms shifts the design implementation task toward embedded software design. When embedded software reaches the complexity typical of today's designs, the risk that the software will not function correctly increases exponentially. The Metropolis project seeks to develop a unified framework that can cope with this challenge.",
	number = "4",
	journal = "Transactions on Computers",
	author = "Felice Balarin and Yosinori Watanabe and Harry Hsieh and Luciano Lavagno and Claudio Passerone and Alberto {Sangiovanni-Vincentelli}",
	year = "2003",
	keywords = "Electronic System Level Design",
	pages = "45--52"
}

@InProceedings{ nikolov_multi-processor_2006,
	address = "Seoul, Korea",
	title = "Multi-processor system design with {ESPAM}",
	isbn = "1-59593-370-0",
	url = "http://portal.acm.org/citation.cfm?id=1176306",
	doi = "10.1145/1176254.1176306",
	abstract = "For modern embedded systems, the complexity of embedded applications has reached a point where the performance requirements of these applications can no longer be supported by embedded system architectures based on a single processor. Thus, the emerging embedded {System-on-Chip} platforms are increasingly becoming multiprocessor architectures. As a consequence, two major problems emerge, i.e., how to design and how to program such multiprocessor platforms in a systematic and automated way in order to reduce the design time and to satisfy the performance needs of applications executed on these platforms. Unfortunately, most of the current design methodologies and tools are based on Register Transfer Level {(RTL)} descriptions, mostly created by hand. Such methodologies are inadequate, because creating {RTL} descriptions of complex multiprocessor systems is error-prone and time {consuming.As} an efficient solution to these two problems, in this paper we propose a methodology and techniques implemented in a tool called Espam for automated multiprocessor system design and implementation. Espam moves the design specification from {RTL} to a higher, so called system level of abstraction. We explain how starting from system level platform, application, and mapping specifications, a multiprocessor platform is synthesized and programmed in a systematic and automated way. Furthermore, we present some results obtained by applying our methodology and Espam tool to automatically generate multiprocessor systems that execute a real-life application, namely a {Motion-JPEG} encoder.",
	booktitle = "Proceedings of the 4th international conference on Hardware/software codesign and system synthesis",
	publisher = "{ACM}",
	author = "Hristo Nikolov and Todor Stefanov and Ed Deprettere",
	year = "2006",
	keywords = "heterogeneous mpsocs, kahn process networks, system-level design",
	pages = "211--216"
}

@Article{ pimentel_systematic_2006,
	title = "A systematic approach to exploring embedded system architectures at multiple abstraction levels",
	volume = "55",
	issn = "0018-9340",
	doi = "{10.1109/TC.2006.16}",
	abstract = "The sheer complexity of today's embedded systems forces designers to start with modeling and simulating system components and their interactions in the very early design stages. It is therefore imperative to have good tools for exploring a wide range of design choices, especially during the early design stages, where the design space is at its largest. This paper presents an overview of the Sesame framework, which provides high-level modeling and simulation methods and tools for system-level performance evaluation and exploration of heterogeneous embedded systems. More specifically, we describe Sesame's modeling methodology and trajectory. It takes a designer systematically along the path from selecting candidate architectures, using analytical modeling and multiobjective optimization, to simulating these candidate architectures with our system-level simulation environment. This simulation environment subsequently allows for architectural exploration at different levels of abstraction while maintaining high-level and architecture-independent application specifications. We illustrate all these aspects using a case study in which we traverse Sesame's exploration trajectory for a {motion-JPEG} encoder application.",
	number = "2",
	journal = "Computers, {IEEE} Transactions on",
	author = "{A.D.} Pimentel and C. Erbas and S. Polstra",
	year = "2006",
	keywords = "analytical modeling, computer architecture, embedded system architecture, Index Terms- Modeling of computer architecture, modeling techniques, {motion-JPEG} encoder, multiobjective optimization, multiple abstraction level, optimisation, performance analysis and design aids., real-time and embedded systems, real-time system, Sesame exploration trajectory, simulation, system-level simulation, system-on-chip",
	pages = "99--112"
}

@Article{ erbas_framework_2007,
	title = "A framework for system-level modeling and simulation of embedded systems architectures",
	volume = "2007",
	url = "http://portal.acm.org/citation.cfm?id=1317034",
	abstract = "The high complexity of modern embedded systems impels designers of such systems to model and simulate system components and their interactions in the early design stages. It is therefore essential to develop good tools for exploring a wide range of design choices at these early stages, where the design space is very large. This paper provides an overview of our system-level modeling and simulation environment, Sesame, which aims at efficient design space exploration of embedded multimedia system architectures. Taking Sesame as a basis, we discuss many important key concepts in early systems evaluation, such as Y-chart-based systems modeling, design space pruning and exploration, trace-driven cosimulation, and model calibration.",
	number = "1",
	journal = "{EURASIP} J. Embedded Syst.",
	author = "Cagkan Erbas and Andy D. Pimentel and Mark Thompson and Simon Polstra",
	year = "2007",
	pages = "2--2"
}

@InProceedings{ sigdel_dse_2008,
	author = "Kamana Sigdel and Mark Thompson and Andy D. Pimentel and Todor Stefanov and Koen Bertels",
	title = "System-Level Design Space Exploration of Dynamic Reconfigurable Architectures",
	booktitle = "SAMOS '08: Proceedings of the 8th international workshop on Embedded Computer Systems",
	year = "2008",
	isbn = "978-3-540-70549-9",
	pages = "279--288",
	location = "Samos, Greece",
	doi = "http://dx.doi.org/10.1007/978-3-540-70550-5\_31",
	publisher = "Springer-Verlag",
	address = "Berlin, Heidelberg"
}

@Article{ eker_taming_2003,
	title = "Taming heterogeneity - the Ptolemy approach",
	volume = "91",
	issn = "0018-9219",
	doi = "{10.1109/JPROC.2002.805829}",
	abstract = "Modern embedded computing systems tend to be heterogeneous in the sense of being composed of subsystems with very different characteristics, which communicate and interact in a variety of ways-synchronous or asynchronous, buffered or unbuffered, etc. Obviously, when designing such systems, a modeling language needs to reflect this heterogeneity. Today's modeling environments usually offer a variant of what we call amorphous heterogeneity to address this problem. This paper argues that modeling systems in this manner leads to unexpected and hard-to-analyze interactions between the communication mechanisms and proposes a more structured approach to heterogeneity, called hierarchical heterogeneity, to solve this problem. It proposes a model structure and semantic framework that support this form of heterogeneity, and discusses the issues arising from heterogeneous component interaction and the desire for component reuse. It introduces the notion of domain polymorphism as a way to address these issues.",
	number = "1",
	journal = "Proceedings of the {IEEE}",
	author = "J. Eker and {J.W.} Janneck and {E.A.} Lee and Jie Liu and Xiaojun Liu and J. Ludvig and S. Neuendorffer and S. Sachs and Yuhong Xiong",
	year = "2003",
	keywords = "component reuse, component-based design, domain polymorphism, embedded computing systems, heterogeneous modeling, hierarchical heterogeneity, modeling environments, models of computation, object-oriented programming, programming environments, Ptolemy, Ptolemy {II, } software architecture, software environment, software reusability",
	pages = "127--144"
}

@Article{ ha_peace_2007,
	title = "{PeaCE:} A hardware-software codesign environment for multimedia embedded systems",
	volume = "12",
	shorttitle = "{PeaCE}",
	url = "http://portal.acm.org/citation.cfm?doid=1255456.1255461",
	doi = "10.1145/1255456.1255461",
	abstract = "Existent hardware-software {(HW-SW)} codesign tools mainly focus on {HW-SW} cosimulation to build a virtual prototyping environment that enables software design and system verification without need of making a hardware prototype. Not only {HW-SW} cosimulation, but also {HW-SW} codesign methodology involves system specification, functional simulation, design-space exploration, and hardware-software cosynthesis. The {PeaCE} codesign environment is the first full-fledged {HW-SW} codesign environment that provides seamless codesign flow from functional simulation to system synthesis. Targeting for multimedia applications with real-time constraints, {PeaCE} specifies the system behavior with a heterogeneous composition of three models of computation and utilizes features of the formal models maximally during the whole design process. It is also a reconfigurable framework in the sense that third-party design tools can be integrated to build a customized tool chain. Experiments with industry-strength examples prove the viability of the proposed technique.",
	number = "3",
	journal = "{ACM} Trans. Des. Autom. Electron. Syst.",
	author = "Soonhoi Ha and Sungchan Kim and Choonseung Lee and Youngmin Yi and Seongnam Kwon and {Young-Pyo} Joo",
	year = "2007",
	keywords = "design-space exploration, hardware-software cosimulation, model-based design",
	pages = "1--25"
}

@InProceedings{ pelkonen_drcf_2003,
	author = "Antti Pelkonen and Kostas Masselos and Miroslav Cup{\'a}k",
	title = "System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC",
	booktitle = "IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing",
	year = "2003",
	isbn = "0-7695-1926-1",
	pages = "174.2",
	publisher = "IEEE Computer Society",
	address = "Washington, DC, USA"
}

@InProceedings{ qu_drcf_2005,
	author = "Yang Qu and Juha-Pekka Soininen",
	title = "SystemC-based Design Methodology for Reconfigurable System-on-Chip",
	booktitle = "DSD '05: Proceedings of the 8th Euromicro Conference on Digital System Design",
	year = "2005",
	isbn = "0-7695-2433-8",
	pages = "364--371",
	doi = "http://dx.doi.org/10.1109/DSD.2005.72",
	publisher = "IEEE Computer Society",
	address = "Washington, DC, USA"
}

@Article{ raabe_rechannel_2008,
	author = "Andreas Raabe and Philipp A. Hartmann and Joachim K. Anlauf",
	title = "ReChannel: Describing and simulating reconfigurable hardware in systemC",
	journal = "ACM Trans. Des. Autom. Electron. Syst.",
	volume = "13",
	number = "1",
	year = "2008",
	issn = "1084-4309",
	pages = "1--18",
	doi = "http://doi.acm.org/10.1145/1297666.1297681",
	publisher = "ACM",
	address = "New York, NY, USA"
}

@Article{ hsiung_perfecto_2008,
	author = "Pao-Ann Hsiung and Chao-Sheng Lin and Chih-Feng Liao",
	title = "Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures",
	journal = "ACM Trans. Reconfigurable Technol. Syst.",
	volume = "1",
	number = "3",
	year = "2008",
	issn = "1936-7406",
	pages = "1--30",
	doi = "http://doi.acm.org/10.1145/1391732.1391737",
	publisher = "ACM",
	address = "New York, NY, USA"
}

@InProceedings{ formaggio_timing-accurate_2004,
	address = "Stockholm, Sweden",
	title = "A timing-accurate {HW/SW} co-simulation of an {ISS} with {SystemC}",
	isbn = "1-58113- 937-3",
	url = "http://portal.acm.org/citation.cfm?id=1016759",
	doi = "10.1145/1016720.1016759",
	abstract = "The paper presents a system level co-simulation methodology for modeling, validating, and analyzing the performance of embedded systems. The proposed solution relies on the integration between an instruction set simulator {(ISS)} and the {SystemC} simulation kernel. In this way, the {ISS} is used to abstract the model of the real programmable device where the {SW} should run, while {SystemC} is used to model {HW} components that interact with the {SW.} A correct validation of such an architecture is infeasible without taking care of timing information. Thus, the paper proposes an effective timing synchronization mechanism, which uses timing information of an {ISS} (or a board) to synchronize the {SystemC} simulation.",
	booktitle = "Proceedings of the 2nd {IEEE/ACM/IFIP} international conference on Hardware/software codesign and system synthesis",
	publisher = "{ACM}",
	author = "Luca Formaggio and Franco Fummi and Graziano Pravadelli",
	year = "2004",
	keywords = "co-simulation, system level modeling",
	pages = "152--157"
}

@Article{ keinert_systemcodesigner_2009,
	title = "{SystemCoDesigner} - an automatic {ESL} synthesis approach by design space exploration and behavioral synthesis for streaming applications",
	volume = "14",
	url = "http://portal.acm.org/citation.cfm?id=1455229.1455230",
	doi = "10.1145/1455229.1455230",
	abstract = "With increasing design complexity, the gap from {ESL} {(Electronic} System Level) design to {RTL} synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable {RTL} code from {C/C++/SystemC-based} input descriptions and software generation for embedded processors is automated as well, an efficient {ESL} synthesis methodology combining both is still missing. This article presents {SystemCoDesigner,} a novel {SystemC-based} {ESL} tool to automatically optimize a hardware/software {SoC} {(System} on Chip) implementation with respect to several objectives. Starting from a {SystemC} behavioral model, {SystemCoDesigner} automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the {SystemC} behavioral model and the behavioral synthesis results. Moreover, {SystemCoDesigner} permits the automatic generation of bit streams for {FPGA} targets from any previously optimized {SoC} implementation. Thus {SystemCoDesigner} is the first fully automated {ESL} synthesis tool providing a correct-by-construction generation of hardware/software {SoC} implementations. As a case study, a model of a {Motion-JPEG} decoder was automatically optimized and implemented using {SystemCoDesigner.} Several synthesized {SoC} variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for {QCIF} streams on a {50MHz} {FPGA.}",
	number = "1",
	journal = "{ACM} Trans. Des. Autom. Electron. Syst.",
	author = "Joachim Keinert and Martin Streub{\textbackslash}\&uhorbar;hr and Thomas Schlichter and Joachim Falk and Jens Gladigau and Christian Haubelt and J{\textbackslash}\&uhorbar;rgen Teich and Michael Meredith",
	year = "2009",
	keywords = "hardware/software codesign, system design",
	pages = "1--23"
}

@InProceedings{ arnout_systemc_2000,
	title = "{SystemC} standard",
	doi = "{10.1109/ASPDAC.2000.835166}",
	abstract = "The emergence and great popularity of system-on-chip {(SoC)} designs has brought with it a variety of suggestions for a single language that can describe all of the functional requirements for those highly complex designs. This paper takes a look at the requirements for system-level design languages and evaluates what it will take for any of these languages to be successful",
	booktitle = "Design Automation Conference, 2000. Proceedings of the {ASP-DAC} 2000. Asia and South Pacific",
	author = "G. Arnout",
	year = "2000",
	keywords = "application specific integrated circuits, circuit {CAD, } functional requirements, {IC} design, integrated circuit design, {SoC} designs, specification languages, system-level design languages",
	pages = "573--577"
}

@Misc{ osci_tlm,
	title = "{TLM2}",
	author = "{Open SystemC Initiative (OSCI)}",
	month = nov,
	year = "2007",
	howpublished = "http://www.systemc.org/"
}

@Article{ ashenden_vhdl_2001,
	title = "{VHDL} standards",
	volume = "18",
	issn = "0740-7475",
	doi = "10.1109/54.953280",
	abstract = "Provides a brief overview of {VHDL-related} standards. The {IEEE} approved the original {VHDL} standard {(IEEE} Std 1076) in 1987, then revised and significantly enhanced it in 1993. In 2000, an interim edition added concurrency control features for shared variables. The new features, called protected types, are based on the idea of monitors seen in concurrent programming languages. The standard is now nearing the final stages of a further revision process, and is headed for approval later this year. This new version is essentially a maintenance revision, with no new language features. The {VHDL} working group has started collecting requirements for language enhancements to be included in the next revision. A task group within the {VHDL} working group is also writing a standard for a programming language interface for {VHDL} simulators and should have a draft ready toward the end of this year ",
	number = "5",
	journal = "Design \& Test of Computers, {IEEE}",
	author = "{P.J.} Ashenden",
	year = "2001",
	keywords = "concurrency control, {IEEE, } {IEEE} standards, programming language interface, protected types, {VHDL} standards, {VHDL} working group",
	pages = "122--123"
}

@Misc{ ieee_standards_????,
	author = "{Standards Education Committee}",
	title = "{SystemVerilog} Standard Tutorial: How {SystemVerilog} Advanced the Verilog {(IEEE} 1364) Standard",
	url = "http://www.ieee.org/portal/cms_docs_iportals/iportals/education/standards/tutorials/systemverilog/3ben-1adv.html",
	howpublished = "http://www.ieee.org/portal/cms\_docs\_iportals/iportals/education/standards /tutorials/systemverilog/3ben-1adv.html"
}

@Book{ gajski_specc_2000,
	edition = "1",
	title = "{SpecC:} Specification Language and Methodology",
	isbn = "0792378229",
	shorttitle = "{SpecC}",
	publisher = "Springer",
	author = "Daniel D. Gajski and Jianwen Zhu and Rainer Domer and Andreas Gerstlauer and Shuqing Zhao",
	month = mar,
	year = "2000"
}

@Book{ black_systemc:ground_2004,
	edition = "1",
	title = "{SystemC:} From the Ground Up",
	isbn = "1402079885",
	shorttitle = "{SystemC}",
	publisher = "Springer",
	author = "David C. Black and Jack Donovan and Bill Bunton and Anna Keist",
	month = may,
	year = "2004"
}

@InProceedings{ doucet_introspection_2003,
	title = "Introspection in {System-Level} Language Frameworks: {Meta-Level} vs. Integrated",
	isbn = "0-7695-1870-2",
	shorttitle = "Introspection in {System-Level} Language Frameworks",
	url = "http://portal.acm.org/citation.cfm?id=789083.1022756",
	abstract = "Reflection and automated introspection of a design in system level design frameworks are seen as necessities for the {CAD} tools to manipulate the designs within the tools. These features are also useful for debuggers, class and object browsers, design analyzers, composition validation, type checking, compatibility checking, etc. However, the central question is whether such features should be integrated into the language, or if we should build frameworks which feature these capabilities in a meta-layer, leaving the system-level language intact. In our recent interactions with designers, we have found differing opinions. Especially in the context of {SystemC,} the temptation to integrate reflective {APIs} into the language is great, because C++ is expressive, and already has type introspective packages available. In this paper, we analyze this issue and show that (i) it is a better {EDA} system architecture to implement reflection/introspection at a meta-layer in a design framework (ii) there are relatively unexplored territories of design automation, such as behavioral typing of component interfaces, corresponding type-theory, and their implication in automating component composition, interface synthesis, and validation, which can be better incorporated if the introspection is implemented at a meta-layer.",
	booktitle = "{DATE} '03: Proceedings of the conference on Design, Automation and Test in Europe",
	publisher = "{IEEE} Computer Society",
	author = "Frederic Doucet and Sandeep Shukla and Rajesh Gupta",
	year = "2003",
	pages = "10382"
}

@Article{ patel_carh_2006,
	title = "{CARH:} service-oriented architecture for validating system-level designs",
	volume = "25",
	issn = "0278-0070",
	shorttitle = "{CARH}",
	doi = "{10.1109/TCAD.2005.857315}",
	abstract = "Existing system-level design languages {(SLDLs)} and frameworks mainly provide a modeling and a simulation framework. However, there is an increasing demand for supporting tools to aid designers in quick and faster design space and architectural exploration. As a result, numerous tools such as integrated development environments {(IDEs)} and others that help in debugging, visualization, validation, and verification are commonly employed by designers. As with most tools, they are targeted for a specific purpose, making it difficult for designers to possess all desired features from one particular tool. Only public-domain tools can be easily extended or interfaced with other existing tools, which a lot of the existing commercial tools do not promote. Having an extendable framework allows designers to implement their own desirable features and incorporate them into their framework. However, for technology reuse and transfer, it is important to have a tidy infrastructure for interfacing the extension with the framework, such that the added solution is not highly coupled with the environment, making distribution and deployment to other frameworks difficult, if not impossible. This requires a plug-and-play framework where features can be easily integrated. These issues of extendibility, deployment, and the inadequacies in {SLDLs} and frameworks are tackled by presenting a service-oriented architecture for validating {SLDs} for {SystemC,} called {CARH,} We code name our software systems after famous computer scientists. {CARH} which uses a variety of open-source technologies such as Doxygen, Apache's Xerces extensible markup language parsers, {SystemC,} and the adaptive communication environment {(ACE)} object request broker.",
	number = "8",
	journal = "{Computer-Aided} Design of Integrated Circuits and Systems, {IEEE} Transactions on",
	author = "{H.D.} Patel and {D.A.} Mathaikutty and D. Berner and {S.K.} Shukla",
	year = "2006",
	keywords = "{CARH, } Common object request broker architecture {(CORBA), } computer debugging, {CORBA, } data visualisation, debugging, distributed object management, embedded system design, integrated development environments, introspection, middleware, open-source technologies, program verification, public domain software, public-domain tools, reflection, service-oriented architecture, validating system-level designs, validation, verification, verification and validation, visualization",
	pages = "1458--1474"
}

@InProceedings{ albertini_computational_2007,
	address = "Salzburg, Austria",
	title = "A computational reflection mechanism to support platform debugging in {SystemC}",
	isbn = "978-1-59593-824-4",
	url = "http://portal.acm.org/citation.cfm?id=1289838",
	doi = "10.1145/1289816.1289838",
	abstract = "System-level and Platform-based design, along with Transaction Level modeling {(TLM)} techniques and languages like {SystemC,} appeared as a response to the ever increasing complexity of electronics systems design, where complex {SoCs} composed of several modules integrated on the same chip have become very common. In this scenario, the exploration and verification of several architecture models early in the design flow has played an important role. This paper proposes a mechanism that relies on computational reflection to enable designers to interact, on the fly, with platform simulation models written in {SystemC} {TLM.} This allows them to monitor and change signals or even {IP} internal register values, thus injecting specific stimuli that guide the simulation flow through corner cases during platform debugging, which are usually hard to handle by standard techniques, thus improving functional coverage. The key advantages of our approach are that we do not require code instrumentation from the {IP} designer, do not need a specialized {SystemC} library, and not even need the {IP} source code to be able to inspect its contents. The reflection mechanism was implemented using a C++ reflection library and integrated into a platform modeling framework. We evaluate our technique through some platform case studies.",
	booktitle = "{CODES+ISSS} '07: Proceedings of the 5th {IEEE/ACM} international conference on Hardware/software codesign and system synthesis",
	publisher = "{ACM}",
	author = "Bruno Albertini and Sandro Rigo and Guido Araujo and Cristiano Araujo and Edna Barros and Willians Azevedo",
	year = "2007",
	keywords = "computational reflection, debugging, platform-based design, system architecture",
	pages = "81--86"
}

@Book{ sobel_introduction_1996,
	title = "An Introduction to {Reflection-Oriented} Programming",
	url = "citeseer.ist.psu.edu/sobel96introduction.html",
	author = "J. Sobel and D. Friedman",
	year = "1996",
	keywords = "Reflection"
}

@InProceedings{ devadithya_c++_2007,
	address = "Norfolk, Virginia",
	title = "C++ reflection for high performance problem solving environments",
	isbn = "1-56555-313-6",
	url = "http://portal.acm.org/citation.cfm?id=1404749",
	abstract = "Problem Solving Environments {(PSE)} in scientific computing domains require the ability to couple High Performance Computing {(HPC)} components. A {PSE} facilitates coupling of tasks or computations in order to aid a scientist in finding a solution to a problem or at least getting closer to a solution. Reflection capabilities are required in order to effectively dynamically couple these components. Reflection facilitates adaptive behavior such as rebinding calls to different functions at run-time, or integrating flexible interpreted languages with compiled languages such as C++ or Fortran. Currently, however, reflection is not available in languages commonly used in high performance computing. While there have been several attempts to incorporate reflection into C++, all of them are either intrusive or are not fully compliant with the C++ standard. In this paper, we present a number of use cases for reflective programming, and show how it can be efficiently and robustly implemented in languages such as C++. Our implementation uses code generation to add metadata, and is fully compliant with the standard C++ specification. We compare the overhead of reflection with languages such as Java, and show that our overhead is acceptable for many scenarios. Our reflection library is open-source, and is available at http://www.extreme.indiana.edu/reflcpp.",
	booktitle = "{SpringSim} '07: Proceedings of the 2007 spring simulation multiconference",
	publisher = "Society for Computer Simulation International",
	author = "Tharaka Devadithya and Kenneth Chiu and Wei Lu",
	year = "2007",
	keywords = "c++ reflection, generic programming, high performance computing, problem solving environments, scientific computing",
	pages = "435--440"
}

@Misc{ roiser_seal_2005,
	title = "{The SEAL C++ Reflection System}",
	url = "http://cdsweb.cern.ch/record/865619",
	howpublished = "http://cdsweb.cern.ch/record/865619",
	author = "S. Roiser and P. Mato",
	year = "2005",
	keywords = "Computing, Computers"
}

@TechReport{ domer_transaction_2006,
	title = "Transaction Level Modeling of Computation",
	url = "http://www.cecs.uci.edu/technical_report/TR06-11.pdf",
	institution = "Center for Embedded Computer Systems University of California, Irvine",
	author = "Rainer Domer",
	month = aug,
	year = "2006"
}

@TechReport{ yu_transaction_2007,
	title = "Transaction Level Platform Modeling in {SystemC} for {Multi-Processor} Designs",
	author = "L. Yu and S. Abdi and D. Gajski",
	year = "2007",
	keywords = "Simulation Platform, {SystemC, } Transaction Level Modeling"
}

@InProceedings{ donlin_transaction_2004,
	title = "Transaction level modeling: flows and use models",
	shorttitle = "Transaction level modeling",
	abstract = "Transaction-level models {(TLMs)} address the problems of designing increasingly complex systems by raising the level of design abstraction above {RTL.} However, {TLM} terminology is presently a subject of contentious debate and a coherent set of {TLM} use-models have not been proposed. In This work we propose a variety of {TLM} use-models that reveal paths through the {TLM} abstraction levels for various types of system. We begin by stating the abstraction levels that comprise 'transaction-level' and identify roles and responsibilities that apply within the use-models. We then take each use-model and discuss the type of system it applies to, the {TLM} abstraction levels it supports, and the design activites applied at those levels. We also consider the distribution of modeling effort between the various design roles and apply that to descriptions of various use-model design flows.",
	booktitle = "{Hardware/Software} Codesign and System Synthesis, 2004. {CODES} + {ISSS} 2004. International Conference on",
	author = "A. Donlin",
	year = "2004",
	keywords = "complex systems, design abstraction, formal verification, large-scale systems, modelling, system design, system verification, {TLM} abstraction levels, {TLM} use-models, transaction level modeling, transaction processing, use-model design flows",
	pages = "75--80"
}

@InProceedings{ vennin_embed_2005,
	title = "Embed scripting inside {SystemC}",
	booktitle = "Forum on specification \& Design Languages - {FDL} 2005",
	author = "J. Vennin and S. Penain and L. Charest and S. Meftali and J. Dekeyser",
	year = "2005",
	keywords = "Python, {SystemC}"
}

@InProceedings{ doucet_environment_2002,
	title = "An Environment for Dynamic Component Composition for Efficient {Co-Design}",
	url = "http://portal.acm.org/citation.cfm?id=874351",
	abstract = "This article describes the Balboa component integrationenvironment that is composed of three parts: a script languageinterpreter, compiled C++ components, and a set {ofSplit-Level} Interfaces to link the interpreted domain to thecompiled domain. The environment applies the notion ofsplit-level programming to relieve system engineers of softwareengineering concerns and to let them focus on systemarchitecture. The script language is a Component {IntegrationLanguage} because it implements a component modelwith introspection and loose typing capabilities. Componentwrappers use split-level interfaces that implement thecomposition rules, dynamic type determination and typeinference algorithms. Using an interface description languagecompiler automatically generates the split-level {interfaces.The} contribution of this work is two fold: an activecode generation technique, and a three-layer environmentthat keeps the C++ components intact for reuse. Wepresent an overview of the environment; demonstrate ourapproach by building three simulation models for an adaptivememory controller, and comment on code generationratios.",
	booktitle = "{DATE} '02: Proceedings of the conference on Design, automation and test in Europe",
	publisher = "{IEEE} Computer Society",
	author = "F. Doucet and S. Shukla and R. Gupta and M. Otsuka",
	year = "2002",
	pages = "736"
}

@InProceedings{ beltrame_exploiting_2006,
	address = "Munich, Germany",
	title = "Exploiting {TLM} and object introspection for system-level simulation",
	isbn = "3-9810801-0-6",
	abstract = "The introduction of Transaction Level Modeling {(TLM)} allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. The simulation speed of {TLM} is orders of magnitude faster than traditional {RTL} simulation; nevertheless, it can become a limiting factor when considering a {Multi-Processor} {System-On-Chip} {(MP-SoC),} as the analysis of these systems can be very complex. The main goal of this paper is to introduce a novel way of exploiting {TLM} features to increase simulation efficiency of complex systems by switching {TLM} models at runtime. Results show that simulation performance can be increased significantly without sacrificing the accuracy of critical application kernels.",
	booktitle = "{DATE} '06: Proceedings of the conference on Design, automation and test in Europe",
	publisher = "European Design and Automation Association",
	author = "G. Beltrame and D. Sciuto and C. Silvano and D. Lyonnard and C. Pilkington",
	year = "2006",
	keywords = "Introspection, Reflection, {StepNP, } Transaction Level Modeling",
	pages = "100--105"
}

@InProceedings{ moy_pinapa:extraction_2005,
	address = "Jersey City, {NJ,} {USA}",
	title = "Pinapa: an extraction tool for {SystemC} descriptions of systems-on-a-chip",
	isbn = "1-59593-091-4",
	shorttitle = "Pinapa",
	url = "http://portal.acm.org/citation.cfm?doid=1086228.1086286",
	doi = "10.1145/1086228.1086286",
	abstract = "{SystemC} is becoming a de-facto standard for the description of complex systems-on-a-chip. It enables system-level descriptions of {SoCs:} the same language is used for the description of the architecture, software and hardware {parts.A} tool like Pinapa is compulsory to work on realistic {SoCs} designs for anything else than simulation: it is able to extract both architecture and behavior information from {SystemC} code, with very few limitations. Pinapa can be used as a front-end for various analysis tools, ranging from ``superlint'' to model-checking. It is open source and available from http://greensocs.sourceforge.net/pinapa/. There exists no equivalent tool for {SystemC} up to now.",
	booktitle = "Proceedings of the 5th {ACM} international conference on Embedded software",
	publisher = "{ACM}",
	author = "Matthieu Moy and Florence Maraninchi and Laurent {Maillet-Contoz}",
	year = "2005",
	keywords = "dynamic, elaboration, front-end, parser, static, systemc",
	pages = "317--324"
}

@InProceedings{ lapalme_.net_2004,
	title = "{.NET} Framework -- A Solution for the Next Generation Tools for {System-Level} Modeling and Simulation",
	isbn = "0-7695-2085-5-1",
	url = "http://portal.acm.org/citation.cfm?id=969017",
	booktitle = "Proceedings of the conference on Design, automation and test in Europe - Volume 1",
	publisher = "{IEEE} Computer Society",
	author = "J. Lapalme and E. M. Aboulhamid and G. Nicolescu and L. Charest and F. R. Boyer and J. P. David and G. Bois",
	year = "2004",
	pages = "10732"
}

@Misc{ _gdb_????,
	title = "{GDB} Debugger",
	url = "http://sourceware.org/gdb/",
	howpublished = "http://sourceware.org/gdb/"
}

@InProceedings{ yang_steering_1997,
	title = "Steering object-oriented scientific computations",
	abstract = "Issues relevant to the steering mechanism for object-oriented scientific computations are examined. The concept of computation steering is delineated, and its benefits are discussed based on past experiences with its application to scientific computations. Experiences of using an object-oriented scripting language called Python to steer C++ applications are presented in further details. It is found that Python and C++ can be combined in an elegant way which combines the benefits of steering and the advantages of using an efficient object-oriented language for scientific modeling",
	booktitle = "Technology of {Object-Oriented} Languages and Systems, 1997. {TOOLS} 23. Proceedings",
	author = "{T.-Y.B.} Yang and G. Furnish and {P.F.} Dubois",
	year = "1997",
	keywords = "C++ application steering, natural sciences computing, object-oriented languages, object-oriented programming, object-oriented scientific computations, object-oriented scripting language, scientific modeling, steering mechanism",
	pages = "112--119"
}

@Article{ paulin_stepnp:system-level_2002,
	title = "{StepNP:} A {System-Level} Exploration Platform for Network Processors",
	volume = "Volume 19",
	shorttitle = "{StepNP}",
	abstract = "The fast-changing communications market requires high-performance yet flexible network-processingplatforms. {StepNP} is an exploratory network processor simulation environment for exploring applications, multiprocessor network-processing architectures, and {SoC} tools. Supporting model interaction, instrumentation, and analysis, the platform lets {R\&D} teams easily add new processors, coprocessors, and interconnects.",
	number = "6",
	journal = "{IEEE} Des. Test",
	author = "Pierre Paulin and Chuck Pilkington and Essaid Bensoudane",
	year = "2002",
	keywords = "multiprocessor system-on-chip, Simulation Platform, {StepNP}",
	pages = "17--26"
}

@Misc{ _gcc-xml_????,
	title = "{GCC-XML}",
	url = "http://www.gccxml.org/HTML/Index.html",
	howpublished = "{http://www.gccxml.org/HTML/Index.html}"
}

@Misc{ _c++/python_????,
	title = "{C++/Python Interfacing: pyplusplus}",
	url = "http://www.language-binding.net/",
	howpublished = "http://www.language-binding.net/"
}

@Misc{ _home_????,
	title = "{Home - Aeroflex Gaisler}",
	url = "http://www.gaisler.com/cms/",
	howpublished = "http://www.gaisler.com/cms/"
}

@InProceedings{ pelkonen_system-level_2003,
	title = "System-level modeling of dynamically reconfigurable hardware with {SystemC}",
	isbn = "1530-2075",
	doi = "{10.1109/IPDPS.2003.1213321}",
	abstract = "To cope with the increasing demand for higher computational power and flexibility, dynamically reconfigurable blocks have become an important part inside a system-on-chip. Several methods have been proposed to incorporate their reconfiguration aspects into a design flow. They all lack either an interface to commercially available and industrially used tools or are restricted to a single vendor or technology environment. Therefore a methodology for modeling of dynamically reconfigurable blocks at the system-level using {SystemC} 2.0 is presented. The high-level model is based on a multi-context representation of the different functionalities that will be mapped on the reconfigurable block during different run-time periods. By specifying the estimated times of context-switching and active-running in the selected functionality modes, the methodology allows us to do true design space exploration at the system-level, without the need to map the design first to an actual technology implementation.",
	booktitle = "Parallel and Distributed Processing Symposium, 2003. Proceedings. International",
	author = "A. Pelkonen and K. Masselos and M. Cupak",
	year = "2003",
	keywords = "active-running, context-switching, dynamically reconfigurable blocks, dynamically reconfigurable hardware, multi-context representation, parallel architectures, system-level modeling, system-on-chip, {SystemC} 2.0",
	pages = "8 pp."
}

@InProceedings{ mehdipour_design_2008,
	address = "Seoul, Korea",
	title = "Design space exploration for a coarse grain accelerator",
	isbn = "978-1-4244-1922-7",
	url = "http://portal.acm.org/citation.cfm?id=1356968",
	abstract = "In the design process of a reconfigurable accelerator employing in an embedded system, multitude parameters may result in remarkable complexity and a large design space. Design space exploration as an alternative to the quantitative approach can be employed to find a right balance between the different design parameters. In this paper, a hybrid approach is introduced to analytically explore the design space for a coarse grain accelerator and determine a wise design point exploiting data extracted from applications, quantitatively. It also provides flexibility for taking into account new design constraints as well as new characteristics of applications. Furthermore, this approach is a methodological approach which reduces the design time and results in a point which satisfies the design goals.",
	booktitle = "Proceedings of the 2008 conference on Asia and South Pacific design automation",
	publisher = "{IEEE} Computer Society Press",
	author = "Farhad Mehdipour and Hamid Noori and Morteza Saheb Zamani and Koji Inoue and Kazuaki Murakami",
	year = "2008",
	pages = "685--690"
}

@InProceedings{ haggard_fpga_2003,
	title = "{A survey of dynamically reconfigurable FPGA devices}",
	booktitle = "Proceedings of the 35th Southeastern Symposium on System Theory (March 16--18, 2003)",
	author = "L.R. Haggard and S. Donthi",
	pages = "422--426",
	year = "2003",
	abstract = "The FPGA market has evolved at an extremely rapid pace, with larger and faster devices being released to the industry by different vendors. One has to select a target FPGA device that snits one's application. This paper presents a survey of currently available dynamically reconfigurable FPGA devices. The devices were: the Atmel AT40k family, the Xilinx Virtex family, the Lattice Semiconductors ORCA and ispXPGA families, and the Altera APEXZOk family. The degree of dynamic reconfigurability of these devices was compared based on partial or full reconfiguration. The architectures of these devices were evaluated based on the granularity and reconfiguration time.",
	keywords = "FPGA, Dynamic Reconfiguration, Programmable Logic"
}

@InProceedings{ rigo_archc:systemc-based_2004,
	title = "{ArchC:} a {SystemC-based} architecture description language",
	isbn = "1550-6533",
	shorttitle = "{ArchC}",
	doi = "{10.1109/SBAC-PAD.2004.8}",
	abstract = "This paper presents an architecture description language {(ADL)} called {ArchC,} which is an open-source {SystemC-based} language that is specialized for processor architecture description. Its main goal is to provide enough information, at the right level of abstraction, in order to allow users to explore and verify new architectures, by automatically generating software tools like simulators and co-verification interfaces. {ArchC's} key features are a storage-based co-verification mechanism that automatically checks the consistency of a refined {ArchC} model against a reference (functional) description, memory hierarchy modeling capability, the possibility of integration with other {SystemC} {IPs} and the automatic generation of high-level {SystemC} simulators. We have used {ArchC} to synthesize both functional and cycle-based simulators for the {MIPS,} Intel 8051 and {SPARC} V8 processors, as well as functional models of modern architectures like {TMS320C62x,} {XScale} and {PowerPC.}",
	booktitle = "Computer Architecture and High Performance Computing, 2004. {SBAC-PAD} 2004. 16th Symposium on",
	author = "S. Rigo and G. Araujo and M. Bartholomeu and R. Azevedo",
	year = "2004",
	keywords = "electronic design automation, formal verification, hardware description languages, high level synthesis, instruction set, instruction sets, logic testing, open-source {SystemC-based} language, processor architecture description language",
	pages = "66--73"
}

@Article{ jondral_cognitive_2005,
	author = "Friedrich K. Jondral",
	title = "Software-defined radio: basics and evolution to cognitive radio",
	journal = "EURASIP J. Wirel. Commun. Netw.",
	volume = "2005",
	number = "3",
	year = "2005",
	issn = "1687-1472",
	pages = "275--283",
	doi = "http://dx.doi.org/10.1155/WCN.2005.275",
	publisher = "Hindawi Publishing Corp.",
	address = "New York, NY, United States"
}

@Misc{ _fpga_????,
	title = "{FPGA and CPLD Solutions from Xilinx, Inc.}",
	url = "http://www.xilinx.com/",
	howpublished = "http://www.xilinx.com/"
}

@Misc{ _coware_????,
	title = "{CoWare}",
	url = "http://www.coware.com/",
	howpublished = "http://www.coware.com/"
}

@Misc{ wiki_electronic_????,
	title = "{Electronic System Level - Wikipedia}",
	howpublished = "http://en.wikipedia.org/wiki/Electronic\_system\_level",
	url = "http://en.wikipedia.org/wiki/Electronic_system_level"
}

@Misc{ wiki_radio_????,
	title = "{Radio - Wikipedia}",
	howpublished = "http://en.wikipedia.org/wiki/Radio",
	url = "http://en.wikipedia.org/wiki/Radio"
}

@Misc{ binary_binutils,
	title = "{BFD - Binary File Descriptor Library}",
	author = "{GNU Binutils}",
	howpublished = "http://www.gnu.org/software/binutils/",
	url = "http://www.gnu.org/software/binutils/"
}

@Misc{ ettus_usrp_????,
	title = "{Ettus Research LLC - Producer of USRP and USRP 2.0}",
	howpublished = "http://www.ettus.com/",
	url = "http://www.ettus.com/"
}

@Misc{ gnu_radio_????,
	title = "{GNU Radio}",
	howpublished = "http://gnuradio.org/",
	url = "http://gnuradio.org/"
}

@Misc{ ossie_radio_????,
	title = "{OSSIE - SCA-Based Open Source Software Defined Radio}",
	howpublished = "http://ossie.wireless.vt.edu/",
	url = "http://ossie.wireless.vt.edu/"
}

@Misc{ acorn_radio_????,
	title = "{Acorn-SDR - A Collaboration of Radio Nodes}",
	howpublished = "http://www.g3ukb.co.uk/",
	url = "http://www.g3ukb.co.uk/"
}

@Misc{ sdr_classif_????,
	title = "{An SDR Classification Model}",
	howpublished = "http://f4dan.free.fr/sdr\_class\_eng.html",
	url = "http://f4dan.free.fr/sdr_class_eng.html"
}

@Misc{ sdr_saqrx_????,
	title = "{SAQ Receiver}",
	howpublished = "http://web.telia.com/$\sim$u33233109/saqrx/saqrx.html",
	url = "http://web.telia.com/~u33233109/saqrx/saqrx.html"
}

@Misc{ fossati_trap,
	title = "{TRAP: TRansaction level Automatic Processor generator}",
	author = "Giovanni Beltrame and Luca Fossati",
	howpublished = "http://code.google.com/p/trap-gen/",
	url = "http://code.google.com/p/trap-gen/"
}

@Misc{ grimeton_web_????,
	title = "{Grimeton VLF Transmitter}",
	howpublished = "http://www.grimeton.org/ENG/HTML\_eng/besoka.html",
	url = "http://www.grimeton.org/ENG/HTML_eng/besoka.html"
}

@Book{ pierpont_morse_2002,
	title = "The Art and Skill of Radio-Telegraphy",
	author = "William G. Pierpont",
	publisher = "eBook",
	address = "http://www.qsl.net/n9bor/n0hff.htm",
	year = "2002"
}

@Misc{ demorse_matlab_????,
	title = "{Demorse at MatLab Central}",
	howpublished = "http://www.mathworks.com/matlabcentral/fileexchange/21491",
	url = "http://www.mathworks.com/matlabcentral/fileexchange/21491"
}

@Book{ frerking_dsp_1994,
	title = "{Digital Signal Processing in Communication Systems}",
	author = "Marvin E. Frerking",
	publisher = "Van Nostrand Reinhold",
	year = "1994"
}

@Misc{ morsegen_web_????,
	title = "{MorseGen - Morse Generator}",
	howpublished = "http://www.g4ilo.com/morsegen.html",
	url = "http://www.g4ilo.com/morsegen.html"
}

@InProceedings{ fossati_resp,
	author = "Giovanni Beltrame and Cristiana Bolchini and Luca Fossati and Antonio Miele and Donatella Sciuto",
	title = "{ReSP: a non-intrusive transaction-level reflective MPSoC simulation platform for design space exploration}",
	booktitle = "ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference",
	year = "2008",
	isbn = "978-1-4244-1922-7",
	pages = "673--678",
	location = "Seoul, Korea",
	publisher = "IEEE Computer Society Press",
	address = "Los Alamitos, CA, USA"
}

@InProceedings{ fossati_hlm,
	author = "Giovanni Beltrame and Luca Fossati and Donatella Sciuto",
	title = "{High-Level Modeling and Exploration of Reconfigurable MPSoCs}",
	booktitle = "AHS '08: Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems",
	year = "2008",
	isbn = "978-0-7695-3166-3",
	pages = "330--337",
	doi = "http://dx.doi.org/10.1109/AHS.2008.15",
	publisher = "IEEE Computer Society",
	address = "Washington, DC, USA"
}

@MastersThesis{ arlati_thesis,
	title = "{System Level Modeling of Dynamically Reconfigurable Systems and its applicationto Software Defined Radio}",
	author = "Fabio Arlati",
	school = "Politecnico di Milano",
	month = "12",
	year = "2009"
}

@Misc{ xilinx_icap,
	title = "{FPGA and CPLD Solutions}",
	author = "{from Xilinx, Inc.}"
}

@InProceedings{ gio_concurrent,
	author = "Giovanni Beltrame and Luca Fossati and Donatella Sciuto",
	title = "{Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design}",
	booktitle = "CODES+ISSS '08: Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis",
	year = "2008",
	isbn = "978-1-60558-470-6",
	pages = "7--12",
	location = "Atlanta, GA, USA",
	doi = "http://doi.acm.org/10.1145/1450135.1450138",
	publisher = "ACM",
	address = "New York, NY, USA"
}

